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fifth generation hexfets from international rectifier utilize advancedprocessing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the to-220 fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. the moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. this isolation is equivalent to using a 100 micron mica barrier with standard to-220 product. the fullpak is mounted to a heatsink using a single clip or by a single screw fixing. s d g parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 14 i d @ t c = 100c continuous drain current, v gs @ 10v 9.8 a i dm pulsed drain current 56 p d @t c = 25c power dissipation 45 w linear derating factor 0.30 w/c v gs gate-to-source voltage 16 v e as single pulse avalanche energy 340 mj i ar avalanche current 8.4 a e ar repetitive avalanche energy 4.5 mj dv/dt peak diode recovery dv/dt 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c mounting torque, 6-32 or m3 srew 10 lbf?in (1.1n?m)
parameter typ. max. units r jc junction-to-case CCC 3.3 r ja junction-to-ambient CCC 65 thermal resistance v dss = 150v r ds(on) = 0.085 ? i d = 14a advanced process technology ultra low on-resistance dynamic dv/dt rating 175c operating temperature fast switching fully avalanche rated lead-free 07/23/04 www.irf.com 1 to-220 fullpak c/w downloaded from: http:///

2 www.irf.com electrical characteristics @ t j = 25c (unless otherwise specified) repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) starting t j = 25c, l = 9.5mh r g = 25 ? , i as = 8.4a. (see figure 12) i sd 8.4a, di/dt 510a/s, v dd v (br)dss , t j 175c. pulse width 300s; duty cycle 2%. caculated continuous current based on maximum allowable junction temperature; for recommended current-handling of thepackage refer to design tip # 93-4. s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode) CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 8.4a, v gs = 0v t rr reverse recovery time CCC 180 270 ns t j = 25c, i f = 8.4a q rr reverse recoverycharge CCC 1130 1700 nc di/dt = 100a/s t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics 14 56 parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 150 CCC CCC v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.18 CCC v/c reference to 25c, i d = 1ma CCC CCC 0.085 v gs = 10v, i d = 8.4a CCC CCC 0.095 ? v gs = 5.0v, i d = 8.4a v gs(th) gate threshold voltage 1.0 CCC 2.0 v v ds = v gs , i d = 250a g fs forward transconductance 14 CCC CCC s v ds = 50v, i d = 8.4a CCC CCC 25 a v ds = 150v, v gs = 0v CCC CCC 250 v ds = 120v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 na v gs = 16v gate-to-source reverse leakage CCC CCC -100 v gs = -16v q g total gate charge CCC CCC 140 i d = 8.4a q gs gate-to-source charge CCC CCC 9.5 nc v ds = 120v q gd gate-to-drain ("miller") charge CCC CCC 53 v gs = 10v, see fig. 6 and 13 t d(on) turn-on delay time CCC 8.3 CCC v dd = 75v t r rise time CCC 20 CCC ns i d = 8.4a t d(off) turn-off delay time CCC 110 CCC r g = 6.2 ?, v gs = 10v t f fall time CCC 53 CCC r d = 8.9 ?, see fig. 10 between lead,6mm (0.25in.) from package and center of die contact c iss input capacitance CCC 1600 CCC v gs = 0v c oss output capacitance CCC 290 CCC pf v ds = 25v c rss reverse transfer capacitance CCC 150 CCC ? = 1.0mhz, see fig. 5 nh i gss s d g l s internal source inductance CCC 7.5 CCC r ds(on) static drain-to-source on-resistance l d internal drain inductance 4.5 i dss drain-to-source leakage current downloaded from: http:///

www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 1 10 100 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 7.0v 5.5v 4.5v 4.0v 3.5v 2.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 2.7v 1 10 100 0.1 1 10 100 20s pulse width t = 175 c j top bottom vgs 15v 10v 7.0v 5.5v 4.5v 4.0v 3.5v 2.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 2.7v 1 10 100 2.0 3.0 4.0 5.0 6.0 7.0 v = 50v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 175 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 14a downloaded from: http:///

4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 1000 v ds , drain-to-source voltage (v) 10 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 20 40 60 80 100 120 140 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 8.4a v = 30v ds v = 75v ds v = 120v ds 0.1 1 10 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 175 c j 1 10 100 1000 v ds , drain-tosource voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1ms 1 0ms operation in this area limited by r ds (on) 100s downloaded from: http:///

www.irf.com 5 fig 10a. switching time test circuit v ds 9 0% 1 0% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms
1 0.1 %
+ - fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 25 50 75 100 125 150 175 0 2 4 6 8 10 12 14 t , case temperature ( c) i , drain current (a) c d 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) downloaded from: http:///

6 www.irf.com q g q gs q gd v g charge d.u.t. v d s i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + -
fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v 25 50 75 100 125 150 175 0 200 400 600 800 1000 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 3.4a 5.9a 8.4a downloaded from: http:///

www.irf.com 7 p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop r e-applied v oltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets
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8 www.irf.com data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 07/04 to-220 full-pak part marking information with assembly example: this is an irfi840g lot code 3432 as s e mbl e d on ww 24 1999 in the assembly line "k" part number lot code assembly int e r nat ional r e ct if ie r logo 34 32 924k irf i840g dat e code year 9 = 1999 week 24 line k note: "p" in assembly line position indicates "lead-free" to-220 full-pak package outline dimensions are shown in millimeters (inches) downloaded from: http:///
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ downloaded from: http:///

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